STV5348
STV5348/H - STV5348/T
MONOCHIP TELETEXT AND VPS DECODER
WITH 8 INTEGRATED PAGES
September 1998
.
COMPLETE TELETEXT AND VPS DECODER
INCLUDING AN 8 PAGE MEMORY ON A SIN-
GLE CHIP
.
UPWARD SOFTWARE COMPATIBLE WITH
PREVIOUS SGS-THOMSON's MULTICHIP
SOLUTIONS (SAA5231, SDA5243, STV5345)
.
PERFORM PDC SYSTEM A (VPS) AND PDC
SYSTEM B (8/30/2) DATA STORAGE SEPA-
RATLY
.
DEDICATED "ERROR FREE" OUTPUT FOR
VALID PDC DATA
.
INDICATION OF LINE 23 FOR EXTERNAL
USE
.
SINGLE +5V SUPPLY VOLTAGE
.
SINGLE 13.875MHz CRYSTAL
.
REDUCED SET OF EXTERNAL COMPO-
NENTS, NO EXTERNAL ADJUSTMENT
.
OPTIMIZED NUMBER OF DIGITAL SIGNALS
REDUCING EMC RADIATION
.
HIGH DENSITY CMOS TECHNOLOGY
.
DIGITAL DATA SLICER AND DISPLAY
CLOCK PHASE LOCK LOOP
.
28 PIN DIP & SO PACKAGE
DESCRIPTION
The STV5348 decoder is a computer-controlled
teletext device including an 8 page internal mem-
ory. Data slicing and capturing extracts the teletext
information embedded in the composite video sig-
nal. Control is accomplished via a two wire serial
I
2
C bus
. Chip address is 22h. Internal ROM pro-
vides a character set suitable to display text using
up to seven national languages. Hardware and
software features allow selectable master/slave
synchronization configurations. The STV5348 also
supports facilities for reception and display of cur-
rent level protocol data.
DIP28
(Plastic Package)
ORDER CODE :
STV5348 West European
STV5348/H East European
STV5348/T Turkish & European
1
2
3
4
5
6
28
27
26
25
24
23
7
8
9
22
21
20
10
19
11
18
12
17
13
16
14
15
ODD/EVEN
COR
BLAN
RGB REF
R
B
G
V
SSD
FFB
STTV/LFB
POL
V
DDA
CVBS
MA/SL
CBLK
TEST
V
SSA
V
SSO
XTI
XTO
V
DDD
VCR/TV
RESERVED
DV
L23
SDA
SCL
Y
5
3
4
8
-0
1
.
EPS
PIN CONNECTIONS
SO28
(Plastic Package)
ORDER CODE :
STV5348D West European
STV5348D/H East European
STV5348D/T Turkish & European
1/22
PIN DESCRIPTION
Pin N
o
Symbol
Function
Description
Figure
1
CVBS
Input
Composite Video Signal Input through Coupling Capacitor
9
2
MA/SL
Input
Master/Slave Selection Mode
11
3
V
DDA
Analog Supply
+5V
-
4
POL
Input
STTV / LFB / FFB Polarity Selection
12
5
STTV/LFB
Output / Input
Composite Sync Output, Line Flyback Input
15
6
FFB
Input
Field Flyback Input
12
7
V
SSD
Ground
Digital Ground
-
8
R
Output
Video Red Signal
13
9
G
Output
Video Green Signal
13
10
B
Output
Video Blue Signal
13
11
RGBREF
Supply
DC Voltage to define RGB High Level
13
12
BLAN
Output
Fast Blanking Output TTL Level
15
13
COR
Output
Open Drain Contrast Reduction Output
15
14
ODD/EVEN
Output
25Hz Output Field synchronized for non-interlaced display
15
15
Y
Output
Open Drain Foreground Information Output
15
16
SCL
Input
Serial Clock Input
16
17
SDA
Input/ Output
Serial Data Input/Output
17
18
L23
Output
Line 23 Identification
15
19
DV
Output
VPS Data Valid
15
20
RESERVED
Test
To be connected to V
SSD
through a resistor
15
21
VCR/TV
Input
PLL Time Constant Selection
15
22
V
DDD
Digital Supply
+5V
-
23
XTO
Crystal Output
Oscillator Output 13.875MHz
14
24
XTI
Crystal Input
Oscillator Input 13.875MHz
14
25
V
SSO
Ground
Oscillator Ground
-
26
V
SSA
Ground
Analog Ground
-
27
TEST
Test
Grounded to V
SSA
11
28
CBLK
Input / Output
To connect Black Level Storage Capacitor
28
53
48
-
0
1
.
T
B
L
L23
18
CTRL
Da
ta
A
ddr
ess
CTRL
Da
ta
A
ddr
ess
Data
Clock
BLAN
RED
GREEN
BLUE
Y
SCL
SDA
XTI
XTO
CVBS
TEST
RGB REF
POL
FFB
STTV/LFB
DISPLAY
INTERFACE
8 PAGES
MEMORY
DATA DECODING
DATA
PROCESSING
CLAMPING
SYNCHRONIZING
DATA EXTRACTION
27
1
28
21
24
23
25
16
17
7
26
14
11
15
10
9
8
13
12
3
22
5
6
2
4
I C BUS
INTERFACE
2
STV5348
CBLK
VCR/TV
V
SSO
V
SSD
V
SSA
ODD/EVEN
COR
V
DDA
V
DDD
MA/SL
OSCILLATOR
FREQUENCY
SYNTHETIZER
TIME BASE
19 DV
20 TEST
5
3
4
8
-0
2
.
EPS
BLOCK DIAGRAM
STV5348 - STV5348/H - STV5348/T
2/22
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
DD
Positive Supply Voltage on V
DDD
and V
DDA
- 0.3, 6.0
V
V
I
Input Voltage (any input)
- 0.3, V
DD
+ 0.5
V
V
O
Output Voltage (any output)
- 0.3, V
DD
+ 0.5
V
V
DD
Difference between V
DDD
, V
DDA
0.25
V
T
oper
Operating Ambient Temperature
0, + 70
o
C
T
stg
Storage Temperature
- 40, + 150
o
C
53
48
-
0
2
.
T
B
L
ELECTRICAL CHARACTERISTICS (V
DD
= 5V, V
SS
= 0V, T
A
= 25
o
C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
SUPPLIES
V
DD
Supply Voltage
4.75
5
5.25
V
I
DDD
V
DDD
Pin Supply Current
30
mA
I
DDA
V
DDA
Pin Supply Current
5
mA
INPUTS
CBLK
I
BLKO
Source Current (V
CBLK
= 2V, V
CVBS
= 0V)
80
A
I
BLKI
Sink Current (V
CBLK
= 2V, V
CVBS
= 1V))
- 10
A
CVBS
CVBSI
Video Input Amplitude (peak to peak)
1
V
CVBSC
Input Capacitance
10
pF
t
SYNC
Delay from CVBS to TCS Output from STTV Pin
200
ns
V
CLAMP
Clamping Level at Synchro Pulse
0
mV
I
CLPH
High Level Clamp Current (CVBS = V
CLAMP
+ 1V)
5
A
I
CLPL
Low Level Clamp Current (CVBS = V
CLAMP
- 0.3V)
- 400
A
MA/SL, POL, LFB, FFB, VCR/TV
V
IL
Input Voltage Low Level
- 0.3
+ 0.8
V
V
IH
Input Voltage High Level
2
V
DD
V
I
IL
Input Leakage Current (V
I
= 0 to V
DDD
)
- 10
+ 10
A
C
I
Input Capacitance
10
pF
SCL, SDA
V
IL
Input Voltage Low Level
- 0.3
+ 1.5
V
V
IH
Input Voltage High Level
3
V
DD
V
I
IL
Input Leakage Current (V
I
= 0 to V
DD
)
- 10
+ 10
A
f
SCL
Clock Frequency (SCL)
100
kHz
t
R
, t
F
Input Rise and Fall Time (10 to 90%)
2
s
C
I
Input Capacitance
10
pF
RGB REF
V
I
Input Voltage
V
DD
- 0.5V
V
DD
V
DD
+ 0.3V
V
I
I
Input Current
50
mA
53
48
-
0
3
.
T
B
L
STV5348 - STV5348/H - STV5348/T
3/22
ELECTRICAL CHARACTERISTICS - V
DD
= 5V, V
SS
= 0V, T
A
= 25
o
C (continued)
Symbol
Parameter
Min.
Typ.
Max.
Unit
OUTPUTS
RGB
V
OL
Output Low Voltage (I
OL
= 2mA)
0.4
V
V
OH
Output High Voltage (I
OH
= -2mA, RGB REF = V
DD
/2)
RGB REF - 0.5
RGB REF
V
C
L
Load Capacitance
50
pF
t
R
, t
F
Rise and Fall Time (10 to 90%)
20
ns
BLAN
V
OL
Output Low Voltage (I
OL
= 2mA)
0
0.4
V
V
OH
Output High Voltage (I
OH
= -0.2mA)
V
DD
- 0.5
V
C
L
Load Capacitance
50
pF
t
R
, t
F
Rise and Fall Time (10 to 90%)
20
ns
ODD/EVEN, STTV, L23, DV
V
OL
Output Low Voltage(I
OL
= 2mA)
0
0.5
V
V
OH
Output High Voltage (I
OH
= -0.2mA)
V
DD
- 0.8
V
DD
V
C
L
Load Capacitance
50
pF
t
R
, t
F
Rise and Fall Time (10 to 90%)
20
ns
COR AND Y (with Pull up to V
DDD
)
V
OL
Output Low Voltage (I
OL
= 2mA)
0
0.5
V
C
L
Load Capacitance
25
pF
t
F
Fall Time (R
L
= 1.2k
, V
DDD
- 0.5V to 1.5V)
50
ns
I
OLL
Output Leakage Current
-10
+10
A
SDA
V
OL
Output Low Voltage (I
OL
= 3mA)
0
0.5
V
t
F
Fall Time (3.0 to 1.0V)
200
ns
C
L
Load Capacitance
400
pF
CRYSTAL OSCILLATOR
XTI, XTO
f
XTAL
Crystal Frequency
13.875
MHz
R
BIAS
Internal Bias Resistance
0.4
1
3
M
C
I
Input Capacitance
7
pF
TIMING
SERIAL BUS (referred to V
IH
= 3V, V
IL
= 1.5V)
t
LOW
t
HIGH
Clock :
q
Low Period
q
High Period
4
4
s
t
SU, DAT
Data Set-up Time
250
ns
t
HD, DAT
Data Hold Time
170
ns
t
SU, STO
Stop Set-up Time from Clock High
4
s
t
BUF
Start Set-up Time following a Stop
4
s
t
HD, STA
Start Hold Time
4
s
t
SU, STA
Start Set-up Time following Clock Low to High Transition
4
s
53
48
-
0
4
.
T
B
L
STV5348 - STV5348/H - STV5348/T
4/22
0 4.66
64
312
291
41
0
0
16.67
56.67
40
m
s
lines 42 to 291 inclusive
(and 355 to 604 inclusive interlaced)
(a) LINE RATE
(b) FIELD RATE
all timings in
m
s
line numbers
LSP
(TCS)
R.G.B.Y
(1)
R.G.B.Y
(1)
5
3
4
8
-0
3
.
EPS
Figure 1 : Display Output Timing
t
BUF
t
HD,STA
t
LOW
t
HIGH
t
SU,STO
t
R
t
SU,STA
t
HD,DAT
t
F
t
SU,DAT
SDA
SCL
SDA
5
3
4
8
-0
4
.
EPS
V
IH
= 3V , V
IL
= 1.5V
Figure 2 : Serial Bus Timing
Output signal on STTV Pin :
VCS when R
1
D
2
= 0
TCS when R
1
D
2
= 1
2
4
POL
MA/SL
+5V
VCS when R
1
D
2
= 0
TCS when R
1
D
2
= 1
POL grounded
POL to V
DD
1
Synchro
Extractor
Line PLL
Line PLL
VCS
R
1
D
2
= "0"
TCS
R
1
D
2
= "1"
Bit R
1
D
2
I
2
C
Control
STTV
53
48
-
0
5
.
E
P
S
Figure 3 : Master Synchronization Mode - Hardware Configuration
STV5348 - STV5348/H - STV5348/T
5/22
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